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1 of 21 011006 features processor-controlled or stand-alone solid- state oscillator frequency changes on the fly dual, low-jitter, synchronous fixed- frequency outputs 2-wire serial interface frequency outputs 4.87khz to 66.666mhz 1.25% variation over temperature and voltage 0.5% initial tolerance nonvolatile freque ncy settings single 2.7v to 3.6v supply no external components power-down mode synchronous output gating standard frequency option note: x denotes package option ds1077lx-40 40.000mhz to 4.87khz ds1077lx-50 50.000mhz to 6.09khz ds1077lx-60 60.000mhz to 7.32khz ds1077lx-66 66.666mhz to 8.13khz contact the factory for the availability of additional frequencies. pin assignments out1 out0 12 3 4 gn d scl ctrl0 ctrl1 sda 87 6 5 v c c pin descriptions out1 - main oscillator output out0 - reference output v cc - power-supply voltage gnd - ground ctrl1 - control pin for out1 ctrl0 - control pin for out0 sda - 2-wire serial data input/output scl - 2-wire serial clock ordering information note: xxx denotes frequency option ds1077lz-xxx 8-pin 150mil so ds1077lu-xxx 8-pin 118mil sop description the ds1077l is a dual-output, programmable, fixe d-frequency oscillator requiring no external components for operation. the ds1077l can be used as a processor-cont rolled frequency synthesizer or as a stand-alone oscillator. th e two synchronous output operating fre quencies are user-adjustable in submultiples of the master frequency through the use of two on-chip programmable prescalers and dividers. the specific out put frequencies chosen are stored in nonvolatile (eeprom) memory. the ds1077l defaults to these values upon power-up. the ds1077l features a 2-wire seri al interface that allows in-cir cuit on-the-fly programming of the programmable prescalers (p0 & p1) a nd divider (n) with the desired va lues being stored in nonvolatile (eeprom) memory. design changes can be accommoda ted in-circuit, on-the-fl y by simply programming different values into the device (or reprogramming previously programmed devices). alternatively, for fixed-frequency applications previous ly programmed devices can be used and no connection to the serial interface is required. preprogrammed devices can be ordered in custome r-requested frequencies. the ds1077l is available in so or sop packages, allowing the generation of a clock signal easily, economically, and using minimal board area. chip-s cale packaging is also available on request. ds1077l 3v econoscillator/divide r www.maxim-ic.com 150mil so 118mil sop downloaded from: http:///
ds1077l 2 of 21 block diagram ds1077l figure 1 programmable n divider control logic (table 1) control logic 2-wire interface div1 0m1 0m0 1m1 1m0 en0 sel0 pdn0 pdn1 control registers scl sda internal oscillator p0 prescaler (m divider) p1 prescaler ( m divider ) 0m0 0m1 1m0 1m1 mux pdn 0 en0 sel0 power-down out0 ctrl0 enable select out1 div1 ctrl1 pdn1 (table 2) mclk power-down enable downloaded from: http:///
ds1077l 3 of 21 overview a block diagram of the ds1077l is shown in figure 1. the ds1077l consists of four major components: 1) internal master oscillator, 2) prescalers, 3) programmable divider, and 4) control registers. the internal oscillator is factory trimmed to provide a master frequency (master clk) that can be routed directly to the outputs (out0 & out1) or through separate prescalers (p0 & p1). out1 can also be routed through an additional divider (n). the prescaler (p0) divides the mast er clock by 1, 2, 4, or 8 to be routed directly to the out0 pin. the prescaler (p1) divides the master clock by 1, 2, 4, or 8 that can be routed to the out1 pin or to the divider (n) input, which is then routed to the out1 pin. the programmable divider (n) divide s the prescaler output (p1) by an y number selected between 2 and 1025 to provide the main output (out1) or it can be bypassed altogether by use of the div1 register bit. the value of n is stored in the n register. the control registers are user-programmable throug h a 2-wire serial interface to determine operating frequency (values of p0, p1, and n) and modes of operation. the regist er values are stored in eeprom and, therefore, only need to be programme d to alter frequencies and operating modes. pin descriptions output 1 (out1) C this pin is the main oscillator output; its frequency is determined by the control register settings for the prescaler p1 (mode bits 1m1 and 1m0) and divider n (div word). output 0 (out0) C a reference output, out0, is taken from th e output of the refe rence-select mux. its frequency is determined by the control register settings for ctrl0 and values of prescaler p0 (mode bits 0m1 and 0m0). (see table 1.) control pin 0 (ctrl0) C a multifunctional input pin that can be selected as a mux select, output enable, and/or a power-down. the user-programmable control regist er values en0, sel0, and pdn0 determine its function. (see table 1.) downloaded from: http:///
ds1077l 4 of 21 table 1 en0 (bit) sel0 (bit) pdn0 (bit) ctrl0 (pin) out0 (pin) ctrl0 function device mode 1 hi-z (out1 and out2) power-down 0 0 0 0 hi-z power-down* active 1 master clk/m 0 1 0 0 master clk mux select active 1 hi-z 1 0 0 0 master clk output enable active 1 hi-z 1 1 0 0 master clk/m output enable active** 1 hi-z (out1 and out2) power-down x 0 1 0 master clk power-down active 1 hi-z power-down x 1 1 0 master clk/m power-down active *this mode is for applications where out0 is not used, but ctrl0 is used as a device shutdown. **default condition control pin 1 (ctrl1) C a multifunctional input pin that can be selected as an output enable and/or a power-down. its function is determined by the user-progra mmable control register value of pdn1. (see table 2.) table 2 pdn1 (bit) ctrl1 (pin) ctrl1 function out 1 device mode 0 0 output enable out clk active* 0 1 output enable hi-z active* 1 0 power-down out clk active 1 1 power-down hi-z (out1 and out2) power-down *default condition note: both ctrl0 and ctrl1 can be config ured as power-downs, they are internally or connected so that either of the control pins may be used to provide a power-down function for the whole device, subject to appropriate settings of the pdn0 and pdn1 register bits. (see table 3.) downloaded from: http:///
ds1077l 5 of 21 table 3 pdn0 (bit) pdn1 (bit) shutdown control 0 0 none* 0 1 ctrl1 1 0 ctrl0 1 1 ctrl0 or ctrl1 *ctrl0 performs a power-down if sel0 and en0 are both 0. (see table 1.) serial data input/output (sda) C input/output pin for the 2-wire serial interface used for data transfer. serial clock input (scl) C input pin for the 2-wire serial interfa ce used to synchroni ze data movement on the serial interface. register functions the user-programmable registers can be programmed by the user to determine the mode of operation (mux), operating frequency (div) and bus settings (bus). details of how these registers are programmed can be found in a later s ection; in this section the functi ons of the registers are described. the register setting are nonvolatile, the values are stor ed automatically or as required in eeprom when the registers are programmed via the sda and scl pins. mux word msb lsb msb lsb name * pdn1 pdn0 sel0 en0 0m1 0m0 1m1 1m0 div1 - - - - - - default setting 0 0 0 1 1 0 0 0 0 0 x x x x x x first data byte second data byte *this bit must be set to zero. div1 (bit) this bit allows the output of the prescaler p1 to be routed directly to the out1 pin (div1 = 1). the n divider is bypassed so the progra mmed value of n is ignored. if div1 = 0 (default) the n divider functions normally. 0m1, 0m0, 1m1, 1m0 (bits) these bits set the prescalers p0 and p1, to divide by 1, 2, 4, or 8. (see table 4.) table 4 0m1 0m0 prescaler p0 divisor m 1m1 1m0 prescaler p1 divisor m 0 0 1 * 0 0 1 * 0 1 2 0 1 2 1 0 4 1 0 4 1 1 8 1 1 8 *default condition downloaded from: http:///
ds1077l 6 of 21 en0 (bit) (default en0 = 1) if en0 = 1 and pdn0 = 0, the ctrl0 pin functions as an output enable for out0, the frequency of the output is determined by the sel0 bit. if pdn0 = 1, the en0 bit is ignored, ctrl0 will function as a power-down, output out0 will always be enabled on power-up, and its frequency is determined by the sel0 bit. if en0 = 0, the function of ctrl0 is determined by the sel0 and pdn0 bits. (see table 1.) s e l 0 (default sel0 = 1) if sel0 = 1 and en0 = pdn0 = 0, the ctrl0 pin de termines the state of th e mux, (i.e., the output frequency of out0). if ctrl0 = 0, the output will be the master clock frequency. if ctrl0 = 1, the output will be the output frequency of the m prescaler. if either en0 or pdn0 = 1, then sel0 deter mines the frequency of out0 when it is enabled. if sel0 = 0, the output will be the master clock frequency. if sel0 = 1, the output will be the output frequency of the m prescaler. (see table 1.) pdn0 (default pdn0 = 0) this bit (if set to 1) causes ctrl0 to perform a power-down function, regardle ss of the setting of the other bits. if pdn0 = 0, the function of ctrl0 is dete rmined by the values of en0 and sel0. note: when en0 = sel0 = pdn0 = 0, ctrl0 also functions as a power-down. this is a special case where all the out0 circuitry is disabled even when the device is powered up. this feature can be used to save power when out0 is not used. (see table 1.) pdn1 (default pdn1 = 0) if pdn1 = 1, ctrl1 will function as a power-down. if pdn1 = 0, ctrl1 functions as an out put enable for out1 only. (see table 2.) notes (on output enable and power-down): 1. both enables are smart and wait for the output to be low before going to hi-z. 2. power-down sequence first disables both outputs before powering down the device. 3. on power-up, the outputs are disabled un til the clock has stabilized (~8000 cycles). 4. the device cannot be prog rammed in power-down mode. 5. a power-down command must persist for at least 2 cycles of the lowest output frequency plus 10 s. div word msb lsb msb lsb n9 n8 n7 n6 n5 n4 n3 n2 n1 n0 x x x x x x first data byte second data byte n these ten bits determine the value of the programmable divider (n). the range of divisor values is from 2 to 1025, and is equal to the programme d value of n plus 2. (see table 5.) downloaded from: http:///
ds1077l 7 of 21 table 5 bit value divisor (n) 0 000 000 000 * 2 0 0 00 0 00 001 3 1 111 111 111 1025 *default condition bus word name wc a2 a1 a0 factory default 0* 0* 0* 0* 0 0 0 0 *these bits are reserved and must be set to zero. a0, a1, a2 (default setting = 000) these are the device select bits that determine the address of the device. wc (default setting wc = 0) this bit determines when/if the eeprom is written to after register contents have been changed. if wc = 0, the eeprom is automatically written after a write register command. if wc = 1, the eeprom is only written when the write command is issued. regardless of the value of the wc bit, when the bus register (a0, a1, a2) is written, the current value in all registers (div, mux, and bus) are immediately written to the eeprom. 2-wire serial data bus the ds1077l supports a bidirectional 2-wire bus and data transmission pr otocol. a device that sends data onto the bus is defined as a transmitter, and a device r eceiving data as a receiver. the device that controls the message is called a master. the devices that are controlled by the master are slaves. the bus must be controlled by a master device th at generates the serial clock (scl), controls the bus access, and generates the start and stop conditions. the ds1077l operates as a slave on the 2-wire bus. connections to the bus are made vi a the open-drain i/o lines, sda and scl. a pullup resistor (5k) is connected to sda. the following bus protocol has been defined (see figure 2): data transfer may be initiated only when the bus is not busy. during data transfer, the data line must remain stable whenever the clock line is high. changes in the data line while the clock line is high will be interpreted as control signals. downloaded from: http:///
ds1077l 8 of 21 accordingly, the following bus conditions have been defined: bus not busy: both data and cloc k lines remain high. start data transfer: a change in the state of the data line from high to low while the clock is high defines a start condition. stop data transfer: a change in the state of the data line from low to high while the clock line is high defines the stop condition. data valid: the state of the data line represents valid da ta when, after a start c ondition, the data line is stable for the duration of the high period of the cl ock signal. the data on the line must be changed during the low period of the clock signal. th ere is one clock pulse per bit of data. each data transfer is initiated with a start condition and termin ated with a stop condition. the number of data bytes transferred between start and stop conditions is not limited, and is determined by the master device. the information is transfe rred byte-wise and each receiver acknowledges with a ninth bit. within the bus specifications, a regular mode (100kh z clock rate) and a fast mode (400khz clock rate) are defined. the ds1077l works in both modes. acknowledge: each receiving device, when addressed, is ob liged to generate an acknowledge after the reception of each byte. the master device must generate an extra clock pulse which is associated with this acknowledge bit. a device that acknowledges must pull down the sda line during the acknowledge clock pulse in such a way that the sda line is stable low during the high period of the acknowledge -related clock pulse. of course, setup and hold time s must be taken into account. when the ds1077l eeprom is being written to, it will not be able to perform additional responses. in this case, the slave ds1077l will send a not acknowledge to any data transfer request made by the master. it w ill resume normal operation when the eeprom operation is complete. a master must signal an end-of-d ata to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. in this case, the slave must leave the data line high to enable the master to generate the stop condition. data transfer on 2-wire serial bus figure 2 msb slave address r/w direction bit sda scl start condition 12 6789 12 89 stop condition or repeated start condition 3 - 8 acknowledgement signal from receiver acknowledgement signal from receiver ack ack repeated if more bytes are transferred downloaded from: http:///
ds1077l 9 of 21 figure 2 details how data transfer is accomplished on the 2-wire bus . depending upon the state of the r/w bit, two types of data transfer are possible: 1) data transfer from a master transmitter to a slave receiver. the first byte transmitted by the master is the slave address. next, follows a numbe r of data bytes. the slave returns an acknowledge bit after each received byte. 2) data transfer from a slave transmitter to a master receiver. the first byte (the slave address) is transmitted by the master. the slave then returns an acknowledge bit. next, follows a number of data bytes transmitted by the slave to the master. the ma ster returns an acknowledg e bit after all received bytes other than the last byte. at the end of the last received byte, a not acknowledge is returned. the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated star t condition. since a repeated start condition is also the beginning of the next serial transfer, the bus will not be released. the ds1077l can operate in the following two modes: 1) slave receiver mode: serial data and clock are received through sda and scl. after each byte is received, an acknowledge bit is transmitted. start and stop conditions are recognized as the beginning and end of a serial transfer. address r ecognition is performed by hardware after reception of the slave address and direction bit. 2) slave transmitter mode: the first byte is received and handled as in the slave receiver mode. however, in this mode, the direction bit will indicate that the transfer direction is reversed. serial data is transmitted on sda by the ds1077l while the se rial clock is input on scl. start and stop conditions are recognized as the begi nning and end of a serial transfer. slave address a control byte is the first byte received following the start condition from the master device. the control byte consists of a four-b it control code; for the ds1077l, this is set as 1011 binary for read and write operations. the next three bits of the control byte are the devi ce select bits (a2, a1, and a0) and can be written to the eeprom. they are used by the master device to select which of eight devices are to be accessed. the select bits are in effect the three least significant bits of the slave address. the last bit of the control byte (r/ w ) defines the operation to be performed. when set to a one a read operation is selected, and when set to a zero a write operation is selected. following the start condition, the ds1077l monitors the sda bus check ing the device type identifier be ing transmitted. upon receiving the 1011 code (changeable with one mask) and appropriate device select bits, th e slave device outputs an acknowledge signal on the sda line. downloaded from: http:///
ds1077l 10 of 21 2-wire serial communi cation with ds1077l figure 3 1 s 1 c0 0 1 wa p sda scl address byte command byte start ds1077l ack stop ds1077l ack send a standalone command c1 c2 c3 c4 c5 c6 c7 a a2 a1 a0 write msb of a two-byte register 1 s c0 0 wa sda scl address byte command byte start ds1077l ack ds1077l ack c1 c2 c3 c4 c5 c6 c7 a d0 ap msbyte stop ds1077l ack d1 d2 d3 d4 d5 d6 d7 1 s c0 0 wa sda scl address byte command byte start ds1077l ack ds1077l ack write to a two-byte register c1 c2 c3 c4 c5 c6 c7 a d0 msbyte d1 d2 d3 d4 d5 d6 d7 a ds1077l ack d0 ap lsbyte stop ds1077l ack d1 d2 d3 d4 d5 d6 d7 1 s c0 0 wa sda scl control byte command byte start ds1077l ack ds1077l ack write a single byte to an addressed register c1 c2 c3 c4 c5 c6 c7 a a0 byte address a1 a2 a3 a4 a5 a6 a7 a ds1077l ack d0 ap data byte stop ds1077l ack d1 d2 d3 d4 d5 d6 d7 byte (n+1) d1 d2 d3 d4 d5 d6 sda scl d7 byte n d1 d2 d3 d4 d5 d6 d7 d0 a ds1077l ack d0 ap stop ds1077l ack 1 s c0 0 wa sda scl control byte command byte start ds1077l ack ds1077l ack write multiple bytes to an addressed register c1 c2 c3 c4 c5 c6 c7 a a0 starting byte address a1 a2 a3 a4 a5 a6 a7 a ds1077l ack d0 a byte n ds1077l ack d1 d2 d3 d4 d5 d6 d7 1 1a 2 a1 a0 1 1a 2 a1 a0 1 1a 2 a1 a0 1 1a 2 a1 a0 downloaded from: http:///
ds1077l 11 of 21 2-wire serial communi cation with ds1077l figure 3 (cont.) 1 s 1 c0 01 w sda scl control byte command byte start ds1077l ack read single byte register or msb from a two-byte register c1 c2 c3 c4 c5 c6 c7 a 1 r 01 rd a control byte repeated start ds1077l ack a ds1077l ack np msbyte stop master nack d1 d2 d3 d4 d5 d6 d0 d7 a2 a1 a0 1a2a1a0 np lsbyte stop master nack d1 d2 d3 d4 d5 d6 d0 sda scl d7 1 s c0 01 w sda scl control byte command byte start ds1077l ack read from a two-byte register c1 c2 c3 c4 c5 c6 c7 a 1 r 01 a control byte repeated start ds1077l ack a ds1077l ack a msbyte master ack d1 d2 d3 d4 d5 d6 d7 d0 1 a2 a1 a0 rd 1a2a1a0 1 s 1 c0 01 w sda scl control byte command byte start ds1077l ack read multiple bytes from an addressed register c1 c2 c3 c4 c5 c6 c7 a a ds1077l ack a2 a1 a0 1 r 01 rd a control byte repeated start ds1077l ack a 1a2a1a0 a0 starting byte address a1 a2 a3 a4 a5 a6 a7 a ds1077l ack np byte n stop master nack d1 d2 d3 d4 d5 d6 d0 d7 byte n d1 d2 d3 d4 d5 d6 sda scl d7 d0 a master ack byte (n+1) d1 d2 d3 d4 d5 d6 d7 d0 a master ack downloaded from: http:///
ds1077l 12 of 21 command set data and control information is r ead from and written to the ds1077l in the format shown in figure 3. to write to the ds1077l, the master will issue the slave address of the ds1077l and the r/ w bit will be set to 0. after receiving an acknowledge, the bus master provides a command protocol . after receiving this protocol, the ds1077l will issue an acknowledge, and th en the master can send data to the ds1077l. if the ds1077l is to be read, the master must send the co mmand protocol as before, and then issue a repeat start condition and then the control byte again, this time with the r/ w bit set to one to allow reading of the data from the ds1077l. the command set for the ds1077l is as follows: access div [01] if r/ w = 0, this command writes to the div register. after issuing this command, the next data byte value is to be written into the div register. if r/ w = 1, the next data byte read is th e value stored in the div register. access mux [02] if r/ w = 0, this command writes to the mux register. after issuing this command, the next data byte value is to be written into the mux register. if r/ w = 1, the next data byte read is th e value stored in the mux register. access bus [0d] if r/ w = 0, this command writes to the bus register. after issuing this command, the next data byte value is to be written into the bus register. if r/ w = 1, the next data byte read is th e value stored in the bus register. write e2 [3f] if wc = 0, the eeprom is automatically written to at the end of each command, this is a default condition. in this case the command write e2 is not needed if wc = 1, the eeprom is written when the write e2 command is issued. on receipt of the write e2 command the contents of the bus, div, and mux registers are written into the eeprom, thus locking in the register settings. exception: the bus, div, and mux registers are always automatically written to eeprom after a write to the bus register regardless of the value of the wc bit. application information power-supply decoupling to achieve best results, decouple the power suppl y with 0.01f and 0.1f high -quality, ceramic, surface- mount capacitors as cl ose as possible to v cc /gnd of the device. surface-m ount components minimize lead inductance, which improves perform ance, and ceramic capacitors tend to have adequate high-frequency response for decoupling applications. current consumption the active supply current can be sign ificantly reduced by disabling out 0 when not required and setting its prescaler to divide by 8. likewise, bypassing out1s divider (and using only the prescaler) also significantly reduces the supply current. downloaded from: http:///
ds1077l 13 of 21 absolute maximum ratings voltage on any pin relative to ground -0.5v to 6.0v operating temperature ra nge -40c to +85c programming temperature range 0 c to +70 c storage temperature range -55c to +125c soldering temperature see j-std-020a specification dc electrical characteristics (t a = -40c to +85c, v cc = 2.7v to 3.6v) parameter symbol condition min typ max units notes supply voltage v cc 2.7 3.6 v 1 high-level output voltage (out1, out0) v oh i oh = -4ma, v cc = min 2.4 v low-level output voltage (out1, out0) v ol i ol = 4ma 0.4 v sda and scl 0.7v cc high-level input voltage v ih ctrl0 and ctrl1 1.4 v cc + 0.3 v sda and scl 0.3v cc low-level input voltage v il ctrl0 and ctrl1 v cc - 0.3 0.6 v high-level input current (ctrl1, ctrl0, sda, scl) i ih v ih = v cc = 3.6v 1 a low-level input current (ctrl1, ctrl0, sda, scl) i il v cc = 3.6v, v il = 0 -1 a supply current (active) ds1077l-66 ds1077l-60 ds1077l-50 ds1077l-40 i cc c l = 15pf (both outputs) (-40 c to +85 c) 30 25 20 15 ma 0 c to +70 c 1 5 standby current (power-down mode) i ccq -40 c to +85 c 10 a downloaded from: http:///
ds1077l 14 of 21 ac electrical characteristics (t a = -40c to +85c, v cc = 2.7v to 3.6v) parameter symbol condition min typ max units notes output frequency tolerance (from nominal) ? f o v cc = 3.15v t a = +25c -0.5 0 +0.5 % 10 over temp (0 c to +70 c) & voltage -1.25 +1.25 over temp (-40 c to +25 c) & voltage -2.4 +1.5 combined freq. variation (from nominal) ? f o over temp (25 c to 85 c) & voltage -1.5 +1.5 % output frequency min output frequency max f out 4.87 66.66 khz mhz 2 power-up time t por + t stab 0.1 1 ms 4 enable out1 from ctrl1 t stab 0.1 1 ms enable out0 from ctrl0 t stab 0.1 1 ms out1 hi-z from ctrl1 t stab 1 ms out0 hi-z from ctrl0 t stab 1 ms load capacitance c l 15 50 pf 3 output duty cycle (out1, out0) 40 60 % output jitter f out = 66mhz m = 1; div1 =1 c l = 12pf 3 sigma pk-to-pk 50 psec 9 downloaded from: http:///
ds1077l 15 of 21 ac electrical characteristics: 2-wire interface (-40 c to +85 c, v cc = 2.7v to 3.6v) parameter symbol condition min typ max units notes fast mode 400 scl clock frequency f scl standard mode 100 khz fast mode 1.3 bus free time between a stop and start condition t buf standard mode 4.7 s fast mode 0.6 hold time (repeated) start condition. t hd : sta standard mode 4.0 s 5 fast mode 1.3 low period of scl t low standard mode 4.7 s fast mode 0.6 high period of scl t high standard mode 4.0 s fast mode 0.6 setup time for a repeated start t su : sta standard mode 4.7 s fast mode 0 data hold time t hd : dat standard mode 0 0.9 s 6, 7 fast mode 100 data setup time t su : dat standard mode 250 ns fast mode 300 rise time of both sda and scl signals t r standard mode 20 + 0.1c b 1000 ns 8 fast mode fall time of both sda and scl signals t f standard mode 20 + 0.1c b 300 ns 8 fast mode 0.6 setup time for stop t su : sto standard mode 4.0 s capacitive load for each bus line c b 400 pf 8 input capacitance c i 5 pf nonvolatile memory characteristics parameter symbol condition min typ max units notes writes +85 c 10,000 downloaded from: http:///
ds1077l 16 of 21 notes: 1) all voltages are referenced to ground. 2) 4.87khz is obtained from a -40mhz standard part. 3) output voltage swings may be impaired at high frequencies combined with high output loading. 4) after this period, the firs t clock pulse is generated. 5) a device must internally provide a hold time of at least 300ns for the sda signal (referred to the v ih min of the scl signal) in order to bridge th e undefined region of the falling edge of scl. 6) the maximum t hd : dat has only to be met if the device does not stretch the low period (t low ) of the scl signal. 7) a fast mode device can be used in a st andard mode system, but the requirement t su : dat > 250ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low peri od of the scl signal, it must output the next data bit to the sda line t r max + t su : dat = 1000 + 250 = 1250ns before the scl line is released. 8) c b total capacitance of one bus line in pf. 9) jitter accumulates over n clock cycl es as: (3 sigma jitter)(no. of cycles) 0.65 . 10) typical frequency shift due to aging is 0.5%. ag ing stressing includes leve l 3 preconditioning with 1000 temperature cycles of - 55c to +125c, 336hr max v cc biased +125c bake. level 3 preconditioning consists of a 24hr +125c storage bake, 192hr moisture soak at +30c/60% r.h., and three solder reflow passes. timing diagram su:sto t t sp hd:sta t t su:sta su:dat t t high r t t low t hd:sta scl start sda stop t buf t f repeated start t hd:dat ordering information: ds1077l master frequency (mhz) 40, 50, 60, 66.66 package type: z = so (150mil) u = sop downloaded from: http:///
ds1077l 17 of 21 typical operating characteristics (v cc = 3.3v, t a = +25oc, unless otherwise specified) supply current (ma) supply current (ma) supply current vs. temperature 6 7 8 9 10 11 12 13 0 1 02 03 04 05 06 07 0 temperature (c) 66mhz device 60mhz device 50mhz device 40mhz device supply current vs. voltage 6 7 8 9 10 11 12 13 14 15 16 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 v cc (v) 66mhz device 60mhz device 50mhz device 40mhz device downloaded from: http:///
ds1077l 18 of 21 typical operating characteristics (cont.) (v cc = 3.3v, t a = +25oc, unless otherwise specified) supply current (ma) supply current (ma) supply current vs. divisor (frequency) 2 2.2 2.4 2.6 2.8 3 3.2 3.4 0 100 200 300 400 500 600 700 800 900 divisor (n) 0c 25c 70c supply current vs. divisor (frequency) 2 2.5 3 3.5 4 4.5 0 100 200 300 400 500 600 700 800 900 divisor (n) 2.7 3 3.6 downloaded from: http:///
ds1077l 19 of 21 downloaded from: http:///
ds1077l 20 of 21 typical operating characteristics (cont.) (v cc = 3.3v, t a = +25oc, unless otherwise specified) shutdown current ( a) ds1077l shutdown current vs. temperature 0.760 0.780 0.800 0.820 0.840 0.860 0.880 0 1 02 03 04 05 06 07 0 temperature (c) 66mhz device frequency change from 25 c (%) ds1077l tempco -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 1 02 03 04 05 06 07 0 temperature (c) -66 device -60 device -50 device -40 device downloaded from: http:///
ds1077l 21 of 21 typical operating characteristics (cont.) (v cc = 3.3v, t a = +25oc, unless otherwise specified) frequency change 3.1v (%) ds1077l voltco -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage (v) -66 device -60 device -50 device -40 device downloaded from: http:///

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